The present disclosure relates to phase-locked loops and, more particularly, to a voltage-controlled oscillator employed in a phase-locked loop.
Phase-locked loops (PLLs) are circuit modules for synchronizing internal clock signals with reference clock signals input from external devices and are used in many electronic circuits.
FIG. 1 is a block diagram of a typical phase-locked loop.
Referring to FIG, 1, a typical PLL is composed of a phase frequency detector (PFD) 101, a charge pump (CP) 102, a low-pass filter (LPF) 103, a voltage-controlled oscillator (VCO) 104, and feedback divider 105. The feedback divider 105 operates to divide an output clock (or oscillation) signal by a predetermined constant and transfer the divided clock signal back to the PFD 101. The PFD 101 compares a feedback clock signal FB_CLK from the feedback divider 105 with a reference clock signal RF_CLK input thereto, and generates up and down signals, UP and DOWN, which are different from each other in phase, on the basis of the compared result.
The CP 102 charges up an output node to raise an output voltage thereof in accordance with the up signal UP that is an output signal of the PFD 101, or discharges down the output node to drop the output voltage thereof. The LPF 103 removes a high-frequency component from the output voltage Vc of the CP 102. The VCO 104 receives the output voltage Vc from the CP 102 through the LPF 103. The VCO 104 generates two clock signals, VCO_out_p and VCO_out_n, which have frequencies corresponding to the input voltage Vc and are contrary to each other in phase by 180°, outputs the clock signals VCO_out_p and VCO_out_n to an external device, and supplies them as a feedback clock signal FB_CLK to the PFD 101 through the feedback divider 105.
FIG. 2 is a circuit diagram of a typical VCO 104 as shown in FIG. 1.
The most important building block is the VCO in the PLL circuit. For a stable operation of the VCO, it is required to set a startup gain at least larger than 1. The VCO 104 shown in FIG. 2 is provided to obtain a high startup gain.
Referring to FIG. 2, the VCO 104 includes a VCO circuit 201. The VCO circuit 201 is a circuit for functioning to permit the oscillation frequency to be controlled by a voltage. The VCO circuit 201 is composed of a PMOS transistor MP1, two inductors L1 and L2, two variable capacitors Cv1 and Cv2, and two transistors MN1 and MN2. The transistors denoted by MP and MN in FIG. 2 are kinds of metal-oxide-semiconductor field effect transistors (MOSFETs).
In the VCO 104, assuming that threshold voltages (Vth) of the transistors are in negative values, a sub-threshold voltage generator 202 is designed to make a voltage at its output node N3 to be slightly higher than Vdd+Vth, where Vth is a threshold voltage and Vdd is a power supply voltage. The sub-threshold voltage generator 202 operates to generate a DC voltage (sub-threshold voltage) to turn off PMOS transistors MP2 and MP3, and outputs the DC voltage to the gates of the transistors MP2 and MP3 respectively through resistors R1 and R2. Thus, the transistors MP2 and MP3 are turned off in response to a DC voltage supplied from the sub-threshold voltage generator 202.
When a control signal En has a low level, for example, 0V, a control signal En_b is set to a high level, for example, Vdd. The control signal En turns off transistor MN5, while the control signal En_b turns on transistor MN4. Because a node N2 is grounded by way of the transistor MN4, a transistor MN3 is turned off. The transistors MP2 and MP3 maintain their turn-off states due to the DC voltage provided from the sub-threshold voltage generator 202. A transistor MP4 is turned on in response to the control signal En having a low level, making a voltage at a node N1 turn to Vdd. Because the present voltage of the node N1 is Vdd, the transistor MP1 is turned off. Thus, there is no current through the transistor MP1 without activation of the VCO 104.
When the control signal En changes from low level, for example, 0V, to high level, for example, Vdd, the transistors MP4 and MN4 are turned off while a transistor MN5 is turned on. During this transition, the transistors MP2 and MP3 still maintain their turn-off states by the DC voltage supplied from the sub-threshold voltage generator 202. According to this condition, a voltage at the node N2 to turn on the transistor MN3 will be determined by a current source Is and a transistor MN6. Once the transistor MN3 is turned on, a voltage of the node N1 becomes 0V causing a large current to flow through the transistor MP1. Therefore, it is possible to increase a startup gain of the VCO 104. Being activated by the current flow through the transistor MP1, the VCO circuit 201 generates the two clock signals VCO_out_p and VCO_out_n, which have frequencies corresponding to the input voltage Vc and are contrary to each other in phase by 180°, by way of resonance with the inductor L1 and the variable capacitor Cv1, and resonance with the inductor L2 and the variable capacitor Cv2.
The two clock signals, VCO_out_p and VCO_out_n, generated from the VCO circuit 201 each contain DC components. Thus, the clock signals, VCO_out_p and VCO_out_n, have any DC components removed therefrom by action of the capacitors C1 and C2, respectively. Then, the clock signals, VCO_out_p and VCO_out_n, without DC components are connected to the gates of the transistors MP2 and MP3 and to the feedback divider 105 of FIG 1. Voltages of the two clock signals VCO_out_p and VCO_out_n are combined with a DC voltage output from the sub-threshold voltage generator 202 and then the combined voltage is applied to gates of the transistors MP2 and MP3. The clock signals, VCO_out_p and VCO_out_n, applied to the gates of the transistors MN2 and MN3 fluctuate up and down on a voltage of the node N3, gradually increasing their amplitude. If the clock signals, VCO_out_p and VCO_out_n, generated from the VCO circuit 201 are increasing in amplitude, the transistors MN2 and MN3 that are turned off would be activated. For instance, the transistors MM2 and MM3 may be turned on when a voltage variation range of the clock signals VCO_out_p and VCO_out_n is lower than Vdd+Vth.
If the transistors MN2 and MN3 are turned on, the voltage of the node N1 gradually increases from its initial voltage 0V, decreasing a current flowing through the transistor MP1. Owing to the reduction of the current flowing through the transistor MP1, the clock signals, VCO_out_p and VCO_out_n, are also reduced in amplitude. As a result, since the VCO 104 forms a negative feedback loop, the amplitude of the clock signals, VCO_out_p and VCO_out_n, is inclined to converge on an adequate value, and will not enlarge indefinitely.
A voltage of the node N1, that adjusts the amount of the current flowing through the transistor MP1, is determined by the currents flowing through the transistors MN3, MP2, and MP3. A gate voltage of the transistor MN3 maintains a constant level, while the gate voltages of the transistors MP2 and MP3 normally fluctuate by the two clock signals VCO_out_p and VCO_put_n output from the VCO circuit 201. Thereby, there would be generated phase noise and jitter. As a result, although the VCO 104 has a high startup gain by a large bias current at an activation time thereof, it effects a large amount of jitter or phase noise.